JOB POSTING INFORMATION
Position Type:	Professional Experience Year Co-op (PEY Co-op: 12-16 months)
Job Title:	Software Engineering Intern Timing, Power, and Modeling
Job Location:	Toronto, ON
Job Location Type:	On-Site
If working on site, can you provide a copy of your COVID-19 safety protocols?:	No
Number of Positions:	1
Salary:	$0.00 hourly for 40.0 hours per week
Start Date:	05/06/2024
End Date:	08/22/2025
Job Function:	Research
Job Description:	The Microchip FPGA Software Engineering team delivers a comprehensive software suite for designing Microchip’s SoC FPGAs and managing the entire design flow from high-level design entry to programming the FPGA part, through synthesis, P&R, timing, power analysis, and simulation.  Within the Software organization, the Timing, Power, and Modeling group is responsible for developing high-quality and user-friendly software for the evaluation of FPGA design performance.  These are key sign-off tools, distributed to a wide range of customers and used internally for the exploration of future FPGA architectures. We research and implement cutting-edge fast and scalable algorithms with the objective of helping FPGA designers achieve timing closure within a strict power budget. To meet these goals, we draw from a variety of computer science domains, including but not limited to: numerical optimization, linear programming, graph theory, modeling non-linear components, large data processing, and machine learning based regression and classification methods. As a member of this R&D team, you will leverage your solid foundations in computer science to develop next generation performance evaluation algorithms.  This internship focuses more particularly on exploring and implementing machine learning models for addressing EDA challenges in performance evaluation and guidance. Location: Toronto office, with guidance from San Jose, California
Job Requirements:	Develop solutions tailored towards supporting very large graph representation. Improve tools' run time to competitive levels. Improve the user experience through guidance tools and context-based help. Integrate some of the capabilities in an internal flow to evaluate future FPGA architectures. Participate to the R&D exploration activities on advanced topics such as OCV, SSTA, IR Drop Help with the enforcement of Microchip’s Software Development Processes Perform design reviews, unit testing, and code reviews Own and sustain product features and provide customer support Continue learning latest EDA discoveries and contribute to the team discussions
Preferred Disciplines:	Computer Engineering Computer Science Electrical Engineering Engineering Science (Electrical and Computer) Engineering Science (Physics) Math & Stats
All Co-op programs:	No
Targeted Co-op Programs:	Targeted Programs Professional Experience Year Co-op (12 - 16 months)

APPLICATION INFORMATION
Application Deadline:	Nov 14, 2023 06:00 AM
Application Receipt Procedure:	Online via system
U of T Job Coordinator:	Ryan Hand

ORGANIZATION INFORMATION
Organization:	Microchip Technology
Division:	FPGA R&D Software Engineering
Website:	www.microchip.com

ADDITIONAL INFORMATION
Length of Workterm:	FLEXIBLE PEY Co-op: 12-16 months (range)