JOB POSTING INFORMATION
Position Type:	Professional Experience Year Co-op (PEY Co-op: 12-16 months)
Job Title:	ASIC Design Engineer (Co-op)
Job Location:	Markham, Ontario
Job Location Type:	On-Site
If working on site, can you provide a copy of your COVID-19 safety protocols?:	Yes
Number of Positions:	Multiple
Salary:	$0.00 hourly for 0.0 hours per week
Start Date:	05/06/2024
End Date:	08/29/2025
Job Function:	Engineering
Job Description:	Overview WHAT YOU DO AT AMD CHANGES EVERYTHING We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.  AMD together we advance_ Responsibilities As a Co-op student, you can make an immediate contribution to AMD's next generation of technology innovations. We have a dynamic, high-energy work environment, filled with expert employees, and unique opportunities for developing your career. You will have the opportunity to connect with AMD leaders, receive one-on-one mentorship, attend amazing networking events, and much more. With AMD, you can get hands-on experience that will give you a competitive edge in the workforce.   LOCATION: Markham, Ontario     ONSITE: This is an on-site role as the hiring team will require the student to work in the office throughout the entire duration of the co-op work term.      PROGRAM TERM: 16-month position from May 6, 2024 – August 29, 2025   WHAT YOU'LL BE DOING Assisting in SOC Static Timing Analysis (STA) for leading Machine Learning CPU/GPU Products: Collaborate closely with SOC (System on Chip) design engineers to aid in the generation of Static Timing Analysis (STA) timing constraints. Focus primarily on state-of-the-art machine learning CPU and GPU products in N2/N3 fabrication process. Utilize both AMD's proprietary in-house design and validation flow as well as established industrial methodologies to ensure precision and compatibility in the STA process.  Verification of Constraint Qualifications for SOC Designs: Work side by side with SOC design engineers and IP designers to ensure the accuracy and validity of the established timing constraints. Facilitate and support the verification process of the constraints to confirm their suitability and robustness for the intended designs. Leverage AMD's specialized in-house validation flow, complemented by industry-standard practices and workflows, to authenticate the constraints' integrity and qualifications. Enhancing Efficiency through Scripting Applications and Flow Development: Engage in the development and optimization of scripting applications tailored to the design and verification processes. Innovate and implement new methodologies and flows to refine and streamline the existing processes, with an emphasis on boosting efficiency and reducing turnaround times. Collaborate with relevant teams to integrate these improvements into the current workflow, ensuring seamless transitions and enhanced productivity. WHAT YOU'LL LEARN You may gain the following experience:  Comprehension of the ASIC Design Flow: Gain a comprehensive understanding of the full industrial-standard ASIC (Application-Specific Integrated Circuit) design flow. Participate actively in one or more stages within this design flow, allowing for hands-on experience and deeper insights into the process.  Mastery of ASIC Timing Verification and Constraint Generation: Strive to become an authority in the domain of ASIC timing verification, ensuring that design specifications meet timing requirements. Specialize in the generation of timing constraints, understanding the details of how they guide and impact the design and validation processes. Expertise in Timing and Constraint Verification Flows & Tools: Develop proficiency in both timing and constraint verification workflows, ensuring that the ASIC design meets the rigorous industry standards. Familiarize oneself with the leading industrial tools utilized in these processes, mastering their applications and features. Introduction to Synthesis Flow and Netlist Concepts: have the chance to explore into the synthesis flow, which is crucial for converting design specifications into a format suitable for physical implementation. Understand the core concepts of both logic and physical netlists, which are representations of the design's components and their interconnections.  Opportunity to Learn Physical Design Flow: Seize the opportunity to immerse oneself in the physical design flow, which revolves around transforming a design's logical representation into its physical layout. Through this, understand how the design is mapped onto the actual silicon, ensuring it aligns with performance, power, and area specifications.
Job Requirements:	KEY QUALIFICATIONS 3rd Year student pursuing a bachelor’s degree in Software Engineering, Computer Science, Computer Engineering or a related discipline Returning to school following the co-op term Written and verbal communication and presentation skills Strong problem-solving and analytical skills with an emphasis on product development PRERRED QUALIFICATIONS Please have knowledge of one or more of the following technical skills:  Demonstrate foundational knowledge in Verilog programming. Proficient in scripting with languages such as Perl and Python, comfortable in the Linux/Unix environment. Possess basic familiarity with the logic and physical design processes. Passionate about diving deep into technical challenges. demonstrate strong organizational, multitasking, analytical, and problem-solving abilities. Exhibit the ability to drive tasks to completion independently. Have excellent verbal and written communication skills.
All Co-op programs:	No
Targeted Co-op Programs:	Targeted Programs Professional Experience Year Co-op (12 - 16 months)

APPLICATION INFORMATION
Application Deadline:	Nov 24, 2023 10:00 PM
Application Receipt Procedure:	Employer Website
Additional Application Information:	https://campuscanada-amd.icims.com/jobs/34886/asic-design-engineer-%28co-op%29/job?mode=view Please select "I intend to apply" before heading to the AMD website.
U of T Job Coordinator:	Ryan Hand

ORGANIZATION INFORMATION
Organization:	AMD (Advanced Micro Devices, Inc.)
Division:	University Relations
Website:	https://www.amd.com/en

ADDITIONAL INFORMATION
Length of Workterm:	FIXED PEY Co-op: 16 months