JOB POSTING INFORMATION
Position Type:	Professional Experience Year Co-op (PEY Co-op: 12-16 months)
Job Title:	ASIC Digital Design Engineering Intern
Job Location:	Toronto/Mississauga OR Napean/Kanata, ON
Job Location Type:	On-Site
If working on site, can you provide a copy of your COVID-19 safety protocols?:	Yes
Number of Positions:	2
Salary:	$36.00 hourly for 40.0 hours per week
Start Date:	05/06/2024
End Date:	08/29/2025
Job Function:	Engineering
Job Description:	Starting in 2024, this 16-month internship position will be with our Solutions Group in Kanata or Nepean (Ottawa) / Toronto or Mississauga (GTA) In CANADA.  What you will learn: The following are examples of tasks that our past interns were involved in: RTL coding, analog block modeling, and writing testbenches in SystemVerilog. Defining synthesis design constraints and resolving STA issues. Defining Clock/Reset domain crossing design constraints. Debugging RTL and gate-level simulation failures. Working at Synopsys, you’ll: Be surrounded by people who are motivated by integrity, execution excellence, leadership, and passion. Make an impact right away by helping our customers solve complex challenges. Help us catalyze Smart Everything, where everything is getting smarter, linked, and safer. Be part of a diverse workforce, where different perspectives, ideas, and backgrounds matter. Be inspired by our “Yes, if” mindset, which drives our employees to challenge themselves and each other to shift perspectives and see what is possible, not impossible, when encountering a challenge. Take pride in making a positive impact on our ecosystem, shareholders, each other, customers, communities, and the planet.   The Solutions Group provides high-quality, silicon-proven semiconductor IP solutions for SoC designs. The Synopsys IP portfolio includes logic libraries, embedded memories, analog IP, wired and wireless interface IP, security IP, embedded processors, and subsystems. To accelerate IP integration, software development, and silicon bring-up, Synopsys’ IP Accelerated initiative provides architecture design expertise, pre-verified and customizable IP subsystems, hardening, signal/power integrity analysis, and IP prototyping kits. Synopsys' extensive investment in IP quality, comprehensive technical support, and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market. At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you. Our Silicon IP business is all about integrating more capabilities into an SoC—faster. We offer the world’s broadest portfolio of silicon IP—predesigned blocks of logic, memory, interfaces, analog, security, and embedded processors. All to help customers integrate more capabilities. Meet unique performance, power, and size requirements of their target applications. And get differentiated products to market quickly with reduced risk. At Synopsys, we’re at the heart of the innovations that change the way we work and play. Self-driving cars. Artificial Intelligence. The cloud. 5G. The Internet of Things. These breakthroughs are ushering in the Era of Smart Everything. And we’re powering it all with the world’s most advanced technologies for chip design and software security. If you share our passion for innovation, we want to meet you.
Job Requirements:	Skill Requirements: Proficient in languages such as C, Verilog, SystemVerilog, Python and Perl. Excellent knowledge of digital design theory. Motivated, eager, and interested in ASIC digital design. Persistence and determination.   Education Requirements: Enrolled in Computer or Electrical Engineering with focus on digital design, semiconductor and related topics. Include your transcripts along with your resume.
Preferred Disciplines:	Electrical Engineering
All Co-op programs:	No
Targeted Co-op Programs:	Targeted Programs Professional Experience Year Co-op (12 - 16 months)

APPLICATION INFORMATION
Application Deadline:	Dec 29, 2023 11:59 PM
Application Receipt Procedure:	Employer Website
If by Website, go to:	https://sjobs.brassring.com/TGnewUI/Search/Home/Home?partnerid=25235&siteid=5359#jobDetails=1999207_5359
Additional Application Information:	47188BR https://sjobs.brassring.com/TGnewUI/Search/Home/Home?partnerid=25235&siteid=5359#jobDetails=1999207_5359 Note from the Engineering Career Centre In addition to applying via the company website, please also click "I intend to apply" so we can track your application.
U of T Job Coordinator:	Nabeela Rahman

ORGANIZATION INFORMATION
Organization:	Synopsys
Division:	Main Office
Website:	https://www.synopsys.com/

ADDITIONAL INFORMATION
Length of Workterm:	FLEXIBLE PEY Co-op: 12-16 months (range)